1. Field of the Invention
The invention relates to a measuring apparatus, and more particularly to an apparatus for measuring the thickness of a gate oxide layer of a vertical transistor and a gate oxide thickness measurement.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. The dynamic random access memory (DRAM) is an important semiconductor device in the information and electronics industry. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells.
Most DRAMs have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 256 megabits. Therefore, integration increases size of the memory cell and the transistor must be reduced yield DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure can reduce the area occupied by memory cells on the semiconductor substrate. Accordingly 3-D capacitors, such as a deep trench capacitors, are applied in the fabrication of the DRAM with capacity of 64 megabits or greater. A conventional DRAM module with a plane transistor covers a larger area of the semiconductor substrate surface and cannot satisfy high integration requirements. Therefore, space saving vertical transistors have become a trend in memory cell fabrication.
However, in vertical transistors, the break down voltage of a gate oxide layer suffers when the width of the active area is altered. Conventional techniques do not provide a method or an apparatus to measure thickness of the gate oxide layer of the vertical transistor.